The invention relates to semiconductor device fabrication, and more particularly, to systems and methods of etching operation management.
Generally, a set of processing steps is performed across a group of semiconductor wafers, typically referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etching process is then performed across the process layer using the patterned layer of photoresist as a mask. The etching process results in the formation of various electronic devices in the process layer. Such electronic devices may be used as, for example, a gate electrode structure for transistors. Many durations, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure. Critical dimensions (CDs), which are the geometries and spacings used to monitor the pattern size and ensure that it is within the customer specification, are especially to have size maintenance during processing. CD bias refers to a situation wherein the designed and actual values do not match. Ideally, CD bias approaches zero, but in actuality can measurably affect the resulting semiconductor device performance and operation.
CD control management is a major challenge in etching processes. Advanced process control (APC) feed-forward or feedback control systems have been widely deployed for after-etch inspection (AEI) and after-development inspection (ADI), as automated methods for monitoring and verifying CD. The APC feed-forward or feedback control systems initiate control scripts, which can be a software program that automatically retrieve the data needed to execute an etch process. For example, large amounts of analysis and/or computations are performed to adjust etching duration on wafers.
In conventional systems, an etching duration is only adjustable by given increments, such as 1, 2 or 3 second increments, resulting in inaccurate adjustment. FIG. 1 is a schematic diagram showing the conventional adjustment for etching duration. If the CD bias is detected as 24.9 nanometers, in an ideal case, the etching duration should be adjusted to approximately 33 seconds. The etching duration, however, can only be adjusted to 32 seconds when using conventional methods.